My research about JIT in inferno-rpi is ended. The cause was obvious but until you does not know about and search through sources, doing debugging, tracing, experimenting – you would not know what it is.
So it is simple – DIS op codes are compiled into ARM machine routines and when compilation is finished it bypasses CPU execution to the address where ARM codes are now. But on the SoC, the instructions cache is not informed automatically that codes about to run are probably in write buffers and not in sync with RAM.
It requires to drain write buffers and invalidate data cache with cachedwbinvse(pos,n) and then invalidate instructions cache with cacheiinvse(pos,n) which I implemented. Those two calls are placed into segflush() which is called by compiler on the end of compilation before bypassing execution there.
JIT is ON
My research about JIT in inferno-rpi is ended. The cause was obvious but until you does not know about and search through sources, doing debugging, tracing, experimenting – you would not know what it is.
So it is simple – DIS op codes are compiled into ARM machine routines and when compilation is finished it bypasses CPU execution to the address where ARM codes are now. But on the SoC, the instructions cache is not informed automatically that codes about to run are probably in write buffers and not in sync with RAM.
It requires to drain write buffers and invalidate data cache with
cachedwbinvse(pos,n)and then invalidate instructions cache withcacheiinvse(pos,n)which I implemented. Those two calls are placed intosegflush()which is called by compiler on the end of compilation before bypassing execution there.JIT is ON now.